This application is based upon and claims priority from prior French Patent Application No. 99-12150, filed Sep. 29, 1999, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention generally relates to electronic memory devices, and more particularly to a serial access type integrated circuit memory, for instance in EEPROM (electrically erasable and programmable read-only memory) or EPROM Flash technology.
2. Description of the Prior Art
The architecture of a serial access memory such as known in the state of the art is depicted schematically in FIG. 1.
The memory first of all comprises a memory plane MM as such. The memory plane is comprised of a matrix of memory cells constructed according to a given technology. A memory cell memorizes the value of one bit of the memory. The cells belonging to a same column are connected to a same connection line, classically depicted vertically and referred to as a bit line. Further, the cells belonging to a same line are connected to a same connection line, classically depicted horizontally and referred to as a word line.
In EEPROM technology, the memory plane is organized in memory words. A memory word designates a certain number of adjacent memory cells on a same line of the memory (for example eight such cells). Such a memory word memorizes eight binary data that form a binary word. A memory word thus memorizes one byte of the memory. In general, at least eight binary data are written into or read from the memory simultaneously, so forming a binary word. In certain cases, the writing is carried out simultaneously in several memory words of a same line of the memory, or even in all the memory words of that line. This is then referred to as page mode writing. In what follows, the term xe2x80x9cwordxe2x80x9d shall be used in isolation to designate sometimes a binary word, sometimes a memory word, depending on the context.
The memory also comprises a line decoder circuit ROWDEC and a column decoder circuit COLDEC, as well as a set of column registers LAT. Each column register is associated to at least one memory word of the memory. When the memory comprises several lines of cells, a column register is in general associated to the memory words of each vertically adjacent line. It comprises eight latches, in which eight data are respectively loaded in view of writing in the associated memory word.
For writing or reading of a binary word in the memory, an instruction is received at a data input DI of the memory in accordance with a given serial transmission protocol (for instance the I2C, SPI or MICROWIRE protocol). Because the binary data of the instruction are sent in the form of an electrical signal, they are in general first of all reshaped by means of an input buffer circuit INBUF. Such a circuit is not obligatory and can be omitted in certain applications. In general, the following information is contained in the instruction: an operating code (e.g. writing or reading), a memory address designating a memory word, and at least one word of data to be written as the case arises (for a write operation). A sequencer SEQ generates command signals adapted to manage the memory appropriately when executing a received instruction. The sequencer SEQ receives a clock signal CLK on a clock input of the memory. The command signals it generates are shown by arrows in broken lines.
Hence the data corresponding to the address of the memory word concerned by the operation are loaded into an address register AREG under control of a sequencer SEQ. From there, a part xi of the memory word address, designated column address, is supplied as an input to the column decoder circuit COLDEC. The latter serves to select the column register associated with the memory word concerned. Another part yj of the memory word address, designated line address, is supplied as an input to the line decoder ROWDEC. The latter serves to select the memory line of the memory word concerned.
Likewise, the data of the instruction corresponding to the data word to be written (as the case arises) are loaded into a first input shift register DREGA under control of the sequencer SEQ. Register DREGA is an eight-bit register, i.e., it comprises eight storage latches in series respectively for memorizing eight consecutively received data. Each latch comprises a non-inverting output which delivers the binary data received at the input, and an inverting output which delivers the inverse binary data relative to the data received at the input. These latches are connected in series via their non-inverting outputs. The shift register DREGA ensures the series-to-parallel conversion of the flow of binary words received by the memory via the input DI. Indeed, the inverting outputs of the eight latches of register DREGA are connected to a data input bus INPUT_DATA_BUS formed by an array of eight respective lines. Bus INPUT_DATA_BUS is also connected to a set of column latches LAT to supply the latter, in parallel form, with eight binary data bits which are the inverse binary bits of the binary data received at the data input DI. These binary data are loaded into storage and switching latches of the column register associated to the memory word concerned under control of the sequencer SEQ. Writing a binary word in an EEPROM technology memory comprises a step of simultaneously erasing all the cells of the memory word (so that they store binary data 1), followed by a step of conditional programming implemented for all the cells of the memory word (such that only the thus conditionally programmed cells store the binary data 0). The erasure and programming of a memory cell in EEPROM technology takes place through the tunnel (xe2x80x9cFowler-Nordheimxe2x80x9d) effect. To this end, a high programming or erasure voltage VPP, on the order of 18 volts, is generated by a generator circuit HVS from the memory supply voltage VCC, which is on the order of 5 volts. The generator circuit HVS is connected to an input terminal Vcc of the memory. This can be a charge pump or a so-called xe2x80x9cSchenkelxe2x80x9d circuit. The high voltage VPP is supplied as an input both to the set LAT and to the ROWDEC circuit.
An operation for reading out a binary word in a given memory word of the memory plane MM calls for a readout circuit SENSE_AMP. Such a circuit comprises eight amplifiers connected, via a readout bus READ_BUS formed by an array of eight lines, respectively to eight storage and switching latches of the column register associated to the memory word concerned. Circuit SENSE_AMP delivers binary data 1 or 0 as a function of whether or not a current is detected in the bit lines concerned of the memory.
The binary data at the output of readout circuit SENSE_AMP are sent in parallel to a second output shift register DREGB via a data bus OUTPUT_DATA_BUS. Shift register DREGB provides a parallel/series conversion of the binary data read in the memory so as to deliver these data in serial form at a data output terminal DO. To this end, the output of the shift register DREGB is connected to output terminal DO via an output buffer circuit OUTBUF. The function of circuit OUTBUF is essentially to amplify an electrical signal carrying the read data and delivered by the terminal DO. Such a circuit is not obligatory however, and can be omitted in certain applications.
One drawback with serial access memories of known architecture is that the first and second shift registers, respectively DREGA and DREGB take up a lot of space on the doped silicon substrate on which the memory is formed. This is due to the large number of transistors that compose them. It will be understood that this area occupied by the shift registers is penalizing in terms of manufacturing costs, especially for low-capacity memories (with few stored bytes).
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.
According to a preferred embodiment of the present invention, a preferred implementation will remedy the drawbacks of prior art memories as discussed above. In view of the foregoing, a preferred embodiment of the present invention proposes an integrated circuit serial access type memory, notably in EEPROM technology, comprising a data input and a data output, a memory plane organized in memory words, as well as a set of column registers, one such register being associated with at least one memory word of the memory, first means operative, during an operation for writing a binary word in a given memory word, for loading the binary data of the binary word received in series at the data input directly into respective storage and switching latches of the column register associated with the memory word and/or second means operative, during an operation for reading a binary word in a memory word, for reading successively the binary data stored in the memory cells of the memory word and for delivering directly, in serial form, each binary data read to the data output of the memory.
The term xe2x80x9cdirectlyxe2x80x9d is to be understood as meaning that the memory according to the invention does not comprise any input shift register and/or output shift register. Nevertheless, it can still comprise an input buffer circuit and/or an output buffer circuit depending on application requirements. In other words, this term means that the data do not undergo a series-to-parallel conversion at the input nor a parallel-to-series conversion at the output. By virtue of the absence of an input shift register and/or an output shift register, the resulting memory occupies a reduced silicon area.